Verilog FSM
Queue control and deterministic state transitions
Personal Project — FPGA & Embedded Systems
FPGA-Based Intelligent Queue Management System
A Verilog FSM and embedded C system built around deterministic timing, hardware-register interfaces, and hardware/software synchronization.
FPGAVerilogEmbedded CFSMValidation
FPGA CONTROLLER — FUNCTIONAL TEST SETUP
01
Overview
The system pairs a Verilog FSM-based FPGA controller with embedded C firmware that interfaces with hardware registers.
02
Hardware
Custom Counters
Hardware-side queue tracking
Hardware Registers
Firmware interface
03
Software / Controls
Embedded C firmware interfaces with the FPGA registers while remaining synchronized with the hardware state machine.
04
Testing
- Wrote functional test cases for normal and fault scenarios.
- Validated hardware/software synchronization and deterministic timing.
- Measured latency against real-time performance requirements.
05
Engineering Challenges
Hardware / Software Synchronization
Kept firmware register access aligned with the FPGA state machine under load.
Deterministic Timing
Verified timing behavior through functional and latency-focused tests.
Fault Handling
Exercised edge cases alongside normal operating scenarios.
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Autonomous Delivery and Retrieval Rover